The physical and electrical characteristics of a memory module (e.g., DDR3 unregistered dual in-line memory module (UDIMM), load-reduced dual in-line memory module (LRDIMM)) are governed by various industry standards documents, typically those promulgated by the Joint Electron Device Engineering Council (JEDEC).
Advancements in an ASIC design and the shrinking operational speed of a memory system have caused a signal delay through a co-processor or I/O (CPIO) device and/or a re-timer (RT) device to grow as a significant percentage of the operating period of a computer system. As used herein, a CPIO encompasses a co-processor or an I/O device both of which are well understood terms.